Television receiver having interlaced scanning with doubled field frequency

ABSTRACT

A television receiver in which a video signal of an interlaced system is received and converted in field frequency by using field memories (6a) and (6b) and then fed to a picture receiving tube (9). In this case, the picture receiving tube (9) is subjected to a vertical deflection scanning by a vertical synchronizing signal of a constant period and the video signal in each field of the video signal to be supplied to the picture receiving tube (9) is delayed by a predetermined time by controlling, for example, the read-out timings of the field memories (6a) and (6b) to thereby keep an interlace-ratio constant. Consequently, since the respective vertical cycles are equal to one another, even if the parabolic current wave of the vertical cycle for deflection correcting, for example, is superposed on the horizontal deflecting current, the horizontal deflection current waveform is equal in each vertical period so that the jitter can be prevented from being produced at the right and left ends of the picture screen.

TECHNICAL FIELD

The present invention relates to a television receiver which displays atelevision picture at, for example, a field frequency twice the normalfield frequency.

BACKGROUND ART

In the existing television system, a so-called interlaced scanningsystem is carried out. That is, one picture (frame) is transmitted bytwo vertical scannings (fields). This interlaced scanning system isconsidered in order to increase the number of scanning lines as much aspossible in a limited frequency band without a flicker being perceivedby a viewer.

However, in the CCIR system employed mainly in European countries, thefield frequency is 50 Hz. By this frequency, the flicker can not beremoved completely and the flicker becomes conspicuous particularly whenthe brightness of the television picture is high.

Therefore, in the prior art, such a television receiver is proposed thata television picture is displayed at a field frequency twice the normalfield frequency. FIG. 1 shows an example thereof.

In the figure, reference numeral 1 designates an antenna, 2 a tuner, 3 avideo intermediate frequency amplifier, and 4 a video detecting circuit.The video detecting circuit 4 produces a video signal Sv of theinterlaced system of, for example, 625 lines/50 fields and 2:1.

This video signal Sv is converted to a digital signal by an A/Dconverter 5 and then fed to a converting circuit 6 so as to be convertedto a field twice normal speed video signal with the field frequencytwice the normal field frequency.

The converting circuit 6 is formed of field memories (random accessmemories each having a storage capacity sufficient for the pictureelements of one field period (1V)) 6a and 6b and switching circuits 6cand 6d. The switching circuit 6c is changed in position to the sides ofthe memories 6a and 6b at every field period 1V, while the switchingcircuit 6d is changed in position reversely. The memory selected by theswitching circuit 6c is supplied with a write clock pulse having atiming corresponding to the above-described picture elements, while thememory selected by the switching circuit 6d is supplied with a readclock pulse with the frequency twice the frequency of the write clockpulse.

The video signal Sv converted to the digital signal by the A/D converter5 is supplied through the switching circuit 6c to the memories 6a and 6bby one field each at every field period 1V in which it is written. Thevideo signal of one field amount, which is written in the memories 6band 6a during a field period 1V just before the above-mentioned fieldperiod, is read out therefrom continuously twice with a cycle of 1/2V.This video signal is derived through the switching circuit 6d. In otherwords, the switching circuit 6d delivers a field twice normal speedvideo signal Sv' with the field frequency.

This video signal Sv' is converted to an analog signal by a D/Aconverter 7 and then fed to a signal processing circuit 8. Then, fromthe signal processing circuit 8, red, green and blue primary colorsignals R, G and B are produced and then supplied to an image receivingtube 9, respectively.

The video signal Sv derived from the video detecting circuit 4 issupplied to a vertical synchronizing separating circuit 10. A verticalsynchronizing signal Pv derived from the separating circuit 10 ismultiplied twice by a frequency multiplyer 11 to be a signal with thefrequency twice the ordinary frequency. This signal is supplied througha vertical deflecting circuit 12 to a deflecting coil 13.

The video signal Sv' derived from the D/A converter 7 is supplied to ahorizontal synchronizing separating circuit 14. A horizontalsynchronizing signal P_(H) ' (having the frequency twice the normalfrequency) derived from the separating circuit 14 is supplied through ahorizontal deflecting circuit 15 to the deflecting coil 13.

Since the example of the television receiver shown in FIG. 1 isconstructed as described above, the primary color signals R, G and Beach of which has the field frequency twice the normal field frequencyare supplied to the picture receiving tube 9 and the horizontal andvertical deflection scannings are carried out at the scanning speedtwice the normal scanning speed, and hence a color picture with thefield frequency twice the normal field frequency is displayed on thepicture receiving tube 9. Accordingly, also in the above CCIR system,the field frequency becomes 100 Hz which is twice the normal fieldfrequency so that the viewer feels no flicker.

In the case of the example shown in FIG. 1, however, the horizontalsynchronization of the video signal Sv' derived from the convertingcircuit 6 is disturbed cyclically so that a distortion occurs in theupper portion of the picture screen.

That is, the write-in state of the video signal Sv derived from thevideo detecting circuit 4 in the memories 6a and 6b is expressed asshown in FIG. 2A, in which references F₁ and F₂ designate first andsecond fields, respectively. The video signal Sv' from the convertingcircuit 6 is expressed as shown in FIG. 2B. In the figure, arrowsrepresent the positions of the vertical synchronizing signals. As willbe clear from FIG. 2B, in the video signal Sv', the phase of thehorizontal synchronization is displaced by 180° at every two fields, orat every 1/50 seconds (shown by broken line arrows), whereby thesynchronization on the upper portion of the picture screen is disturbed,resulting in a picture distortion.

Therefore, the present applicant has proposed a television receiverwhich is free of such picture distortion and FIG. 3 shows an examplethereof. In FIG. 3, like parts corresponding to those of FIG. 1 aremarked with the same references.

In the figure, the video signal Sv derived from the video detectingcircuit 4 is converted to the digital signal by the A/D converter 5 andthen fed to a converting circuit 16 so as to be converted to the fieldtwice normal speed video signal with the frequency twice the normalfield frequency.

The converting circuit 16 is formed of field memories (random accessmemories) 16a and 16b having storage capacities of picture elements of313 horizontal periods (313H) and 312 horizontal periods (312H) andswitching circuits 16c and 16d . The switching circuit 16 is changed inposition alternately to the side of the memory 16a during each period of313H and to the side of the memory 16b during each period of 312H, whilethe switching circuit 16d is changed in position in the reverse manner.These change-overs of the change-over switches 16c and 16d arecontrolled by a control circuit 17. This control circuit 17 is suppliedwith horizontal and vertical synchronizing signals P_(H) and P_(V) whichare separated from the video signal Sv by a synchronizing separatingcircuit 18.

The memory selected by the switching circuit 16c is supplied with thewrite clock pulse having the timing corresponding to the above pictureelements, while the memory selected by the switching circuit 16d issupplied with a read clock pulse with the frequency twice the frequencyof the write clock pulse.

The video signal Sv converted to the digital signal by the A/D converter5 is supplied through the switching circuit 16c to the memories 16a and16b in which it is alternately written during each period of 313H and312H. FIG. 4A shows the write-in state of the memories 16a and 16b, inwhich references F₁ and F₂ represent the first and second fields,respectively. During the periods of 313H and 312H in which the videosignal is being written in one of the memories, the video signal writtenin the other of the memories 16b and 16a during the periods just beforethe above 312H and 313H are read out therefrom twice continuously. Thissignal is derived through the switching circuit 16d as a field twicenormal speed video signal Sv*. FIG. 4B shows the video signal Sv* whichis derived through the switching circuit 16d, in which the fieldportions corresponding to those of FIG. 4A are marked with the samereferences. By the way, due to the difference between the write time andthe read time, extra or lack of one line amount per field is produced inthe video signal Sv*.

In FIG. 4B, at the portions of, for example, the F₁ and F₁ fields (theportions read out from the memory 16a), 313 lines are not read outbecause of a time relation. Further, at, for example, the F₂ and F₂field portions (the portions read out from the momory 16b), the videosignal of one line amount is lacked and during that period, the readingoperation is stopped and the video signal of one line amount is missing(shown by one-dot chain lines). The extra and lack of the video signalof one line amount as mentioned above occur in the vertical blankingperiod so that in practice, this does not disturb the televisionpicture.

The writing in and reading out from the memories 16a and 16b arecontrolled by the control circuit 17.

The video signal Sv* derived from the switching circuit 16d is convertedto the analog signal by the D/A converter 7 and then fed to the signalprocessing circuit 8. Then, the red, green and blue primary colorsignals R, G and B are produced from the signal processing circuit 8 andthen fed to the picture receiving tube 9, respectively.

The control circuit 17 produces a vertical synchronizing signal Pv* atthe timing shown by arrows in FIG. 4B. More particularly, the verticalsynchronizing signal Pv* is produced at the beginning of the first F₁field, at the timing after 312 lines from the preceding line, namely, atthe beginning of the second F₁ field, at the timing after 311.5 linesfrom the preceding line, at the timing after 313 lines from thepreceding line and at the timing after 313.5 lines from the precedingline, or the beginning of the first F₁ field, hereinafter similarly.This synchronizing signal Pv* is supplied through the verticaldeflecting circuit 12 to the deflecting coil 13 by which the verticaldeflection scanning is carried out. When the synchronizing signal Pv* isproduced at the above-mentioned timing, in the same F₁ field and F₂field , the scanning lines are formed at the same positions and thescanning lines respectively formed at the F₁ field and F₂ field aredisplaced by 1/2 scanning line spacing each. In other words, theinterlaced relation of the video signal Sv is kept as it is.

The video signal Sv* from the D/A converter 7 is supplied to thehorizontal synchronizing separating circuit 14. A horizontalsynchronizing signal P_(H) * (having the frequency twice the normalfrequency) derived from the separating circuit 14 is supplied throughthe horizontal deflecting circuit 15 to the deflecting coil 13 by whichthe horizontal deflection scanning is carried out.

According to the example of the television receiver shown in FIG. 3, thehorizontal synchronization of the video signal Sv* becomes continuous asshown in FIG. 4B so that the synchronization can be prevented from beingdisturbed by the insuccessive horizontal synchronization unlike theexample of FIG. 1 and thus no picture distortion is produced.

However, in the example of FIG. 3, since the generation timing of thevertical synchronizing signal Pv* is determined such that the scanninglines of the same F₁ fields and F₂ fields are formed at the samepositions (see the arrows in FIG. 4B), the vertical cycle is madedifferent very slightly and not becomes exactly 1/100 seconds=10 m sec.

By the way, in the television receiver, in order to correct left andright pincushion distortions, a parabolic wave current with the verticalsynchronizing frequency is superposed on the horizontal deflectioncurrent. In this case, since the cycle of the vertical synchronizingsignal Pv* is different (see FIG. 5A) as mentioned above, also thevertical deflection current becomes correspondingly different (see FIG.5B). Further, the horizontal deflection current waveform is changed atevery vertical cycle (see FIG. 5C). As described above, since thehorizontal deflection current waveform is different, a jitter appears inthe right and left ends of the picture screen at a fundamental frequencyof 25 Hz (four field cycles of F₁, F₁, F₂, and F₂). This jitter becomesconspicuous much if the deflection angle becomes larger.

To remove this jitter, it may be considered to correct the horizontaldeflection current waveform by the deflecting system. However, thecorrection thereof is very difficult and requires a special deflectioncorrecting circuit.

In this case, since the cycle of the vertical synchronizing signal Pv*becomes different (see FIG. 5A), also the vertical deflecting currentbecomes different at every vertical cycle (see FIG. 5B) but this doesnot exert so serious bad influence on the picture screen.

DISCLOSURE OF INVENTION

The present invention is to prevent a jitter from being produced at theright and left ends of a picture screen without providing a specialdeflection correcting circuit. To achieve this object, this invention isto provide a television receiver in which a video signal of theinterlaced system is received, its field frequency is converted by usinga field memory and then the video signal is fed to a picture receivingtube. In this case, in the picture receiving tube the verticaldeflection scanning is performed by the vertical synchronizing signal ofa constant cycle and a video signal in each field of the video signalsupplied to the picture receiving tube is delayed by a predeterminedtime so as to keep the interlace-ratio constant.

The television receiver of the present invention is constructed asdescribed above and since each vertical period is equal to one another,the horizontal deflecting current waveforms become equal to one anotherin each vertical cycle. As a result, the jitter can be prevented frombeing produced at the right and left ends of the picture screen.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 and 3 are respectively diagrams showing prior art examples,FIGS. 2A, 2B, 4A, 4B, 5A, 5B are respectively diagrams useful forexplaining the prior art examples, FIG. 6 is a diagram showing anembodiment of a television receiver according to the present invention,FIGS. 7A, 7B and 8A-8F are respectively diagrams useful for theexplanation thereof, FIGS. 9, 10, 12, 13, and 14 are respectivelydiagrams showing other embodiments of the television receiver accordingto the present invention, and FIGS. 11A and 11B are diagrams useful forexplaining the embodiments of FIGS. 9 and 10.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the television receiver according to the presentinvention will hereinafter be described with reference to FIG. 6 In FIG.6, like parts corresponding to those of FIG. 1 are marked with the samereferences and the description thereof will be omitted.

In the embodiment of FIG. 6, the change-over of the switching circuits6c and 6d and the writing-in operation to the memories 6a and 6b arecarried out similarly to those of the example shown in FIG. 1 but byvirtue of the control of a memory control circuit 19, the reading outtiming from the memories 6a and 6b are controlled so that from theswitching circuit 6d derived is a field twice normal speed video signalS_(VN) ' shown in FIG. 7B. That is, one-dot chain lines in FIG. 7Bindicate signal-missing portions. In this case, of the first and secondF₁ fields read out from the memory 6a, the second F₁ field is read outwith a delay of 0.25 H (corresponding to 0.5 line), while of the firstand second F₂ fields read out from the memory 6b, the first F₂ field isread out with a delay of 0.25 H (corresponding to 0.5 line).

This video signal S_(VN) ' is supplied through the D/A converter 7 tothe signal processing circuit 8.

Further, the video signal S_(VN) ' derived from the D/A converter 7 issupplied to the horizontal synchronizing circuit 14. A horizontalsynchronizing signal P_(HN) ' (having the frequency twice the ordinaryfrequency) therefrom is supplied through the horizontal synchronizingcircuit 15 to the deflecting coil 13.

FIG. 7A shows a write-in state of the memories 6a and 6b, in whicharrows indicate the positions of the vertical synchronizing signal PVfrom the vertical synchronizing separating circuit 10.

Further, arrows in FIG. 7B show the positions of signals which aresupplied from the multiplier 11 to the vertical deflecting circuit 12.It is natural that the cycles thereof are equal to one another.

In FIG. 6, reference numeral 20 designates a deflection correctingcircuit which corrects, for example, the pincushion distortion and thiscircuit permits a parabolic wave current of the vertical synchronizingfrequency for correcting the pincushion distortion to be superposed uponthe horizontal deflection current.

Other circuit elements are arranged similarly to those of the exampleshown in FIG. 1.

FIG. 8D shows the scanning line arrangement and the field arrangement inthe embodiment of FIG. 6. In FIGS. 8A-8F, black circles and whitecircles respectively indicate scanning lines. In the embodiment of FIG.6, since the second F₁ ; field is read out with a delay of 0.25 H, thescanning line in the second F₂ field is formed at the lower side of thescanning line in the first F₁ field with a displacement of 1/2 scanningline interval. Further, since the reading of the first F₂ field iscarried out with a delay of 0.25 H, the scanning line in the first F₂field is formed at the lower side of the scanning line in the second F₂field with a displacement of 1/2 scanning line interval.

Whereas, FIG. 8A shows the scanning line arrangement and the fieldarrangement formed by the video signal S_(V). FIG. 8B shows the likearrangement made by the example of FIG. 1 or 3. Further, FIG. 8C showsthe scanning line arrangement and the field arrangement provided for theline multiple speed system in which the two scanning lines by the samesignal are continued each. As will be clear from these figures, thesynthesis of the first and second F₁ fields of the example of FIG. 6 isequivalent to the F₁ field of the line multiple speed system and thesynthesis of the first and second F₂ fields in the example of FIG. 6becomes equivalent to the F₂ field of this multiple speed system. Inother words, the example of FIG. 6 is equivalent to the case where thescanning order of the signal of the previously proposed line multiplespeed system is changed such that the signal of 625 lines/50 fields ofthe non-interlaced system is converted to the signal of the interlacedsystem with the 312.5 lines/100 fields and 2:1.

According to the television receiver of the embodiment of FIG. 6, sincethe cycles of the signal to be supplied to the vertical deflectingcircuit 12 are equal, the respective vertical periods become equal toone another. Thus, the horizontal deflecting current waveforms on whichthe parabolic wave current of the vertical synchronizing frequency forcorrecting the left and right pincushion distortions are superposed areequal to one another during each vertical period. Thus unlike theexample of FIG. 3, there occurs no disadvantage that the jitter isproduced at the left and right ends of the picture screen and so on.Further, since the interlace-ratio is kept constant, it is possible toobtain a good picture image. Furthermore, according to the embodiment ofFIG. 6, since the reading of the second F₁ field is carried out with adelay of 0.25 H and the reading of the first F₂ field is carried outwith a delay of 0.25 H, similarly to the example of FIG. 3, thecontinuity of the horizontal synchronization can be kept and noparticular problem is caused.

FIG. 9 is a diagram showing another embodiment of the televisionreceiver according to the present invention. In this figure, like partscorresponding to those of FIGS. 1 and 6 are marked with the samereferences and will not be described in detail.

In the embodiment of FIG. 9, the read timing from the memories 6a and 6bare not controlled but a delay line is used.

In the embodiment of FIG. 9, the change over of the switching circuits6c and 6d and the writing in and/or reading out from the memories 6a and6b are carried out similarly to the example of FIG. 1 so that from theswitching circuit 6d, there is derived a field twice normal speed videosignal S_(V) ' as shown in FIG. 2B.

In this embodiment of FIG. 9, the video signal S_(V) ' converted to theanalog signal by the D/A converter 7 is supplied to one fixed contact21a of a switching circuit 21 and also through a delay line 22 having adelay time of 0.25H (corresponding to 0.5 line) to the other fixedcontact 21b thereof. This switching circuit 21 is changed in position tothe side of the contact 21a during the first F₁ field and the second F₂field, while it is changed in position to the side of the contact 21bduring the second F₁ ; field and the first F₂ field of the video signalS_(V) '. Accordingly, from this switching circuit 21, there is derivedthe video signal S_(VN) ' (shown in FIG. 7B) similar to the embodimentof FIG. 6, which then is fed to the signal processing circuit 8.

The video signal S_(VN) ' from the switching circuit 21 is supplied tothe horizontal synchronizing separating circuit 14.

The other elements are arranged similarly to those of the examples ofFIGS. 1 and 6.

As a result, also in accordance with the embodiment of FIG. 9, thedisplay similar to that of the embodiment of FIG. 6 can be made and thussimilar action and effect can be achieved.

Next, FIG. 10 is a diagram showing other embodiment of the televisionreceiver according to the present invention, in which like partscorresponding to those of FIG. 3 are marked with the same references andwill not be described in detail.

In the embodiment of FIG. 10, the change over of the switching circuits16c and 16d and the write-in operation in the memories 16a and 16b arecarried out similarly to those of the embodiment of FIG. 3 but the readtiming from the memories 16a and 16b is controlled by the controlcircuit 17 so that from the switching circuit 16d derived is a fieldtwice the normal speed video signal S_(VN*) shown in FIG. llB. That is,a one-dot chain line in FIG. llB indicates a signal lacked portion andthe first and second F₂ fields are read out from the memory 16b with adelay of 0.5 H (corresponding to one line).

This video signal S_(VN*) is supplied through the D/A converter 7 to thesignal processing circuit 8.

Further, the video signal S_(VN*) derived from the D/A converter 7 issupplied to the horizontal synchronizing separating circuit 14. Ahorizontal synchronizing signal P_(HN*) (having the frequency twice thenormal frequency) therefrom is supplied through the horizontaldeflecting circuit 15 to the deflecting coil 13.

FIG. llA shows the write-in state of the memories 16a and 16b , in whichthe arrows indicate the positions of the vertical synchronizing signalP_(V) from the synchronizing separating circuit 18.

In the embodiment of FIG. 10, from the control circuit 17, the verticalsynchronizing signal P_(VN*) which is produced at the timing shown bythe arrows of FIG. llB is supplied to the vertical deflecting circuit12. That is, the vertical synchronizing signal P_(VN*) is produced atthe timing of the beginning of the first F₂ field, at the timing with adelay of 312.5 lines after the preceding timing, at the timing with adelay of 312.5 lines after the preceding timing, at the timing with adelay of 312.5 lines after the preceding timing, and at the timing witha delay of 312.5 lines after the preceding timing, or at the timing ofthe beginning of the first F₂ field and at the similar timinghereinafter. In this way, the respective cycles of the verticalsynchronizing signal P_(VN*) in the embodiment of FIG. 10 are equal toone another.

In FIG. 10, reference numeral 20 designates a deflection correctingcircuit which is used to correct, for example, the pincushion distortionand this deflection correcting circuit is the same as that used in theembodiment of FIG. 6.

The other circuit elements are formed similar to those of the embodimentof FIG. 3.

FIG. 8E shows the scanning line arrangement and the field arrangement inthe embodiment of FIG. 10. In the example of FIG. 11, the timing atwhich the vertical synchronizing signal P_(VN*) is produced is exactlythe same as mentioned above and the reading of the first and second F₂fields is carried out with a delay of 0.5 H so that the scanning line inthe first F₁ field and the scanning line in the first F₂ field areformed at the same position, the scanning line in the second F₁ field isformed at the upper side of the scanning line in the first F₁ field witha displacement of 1/2 scanning line interval, and the scanning line inthe second F₂ field is formed at the lower side of the scanning line ofthe first F₂ field by the displacement of 1/2 scanning line interval.

The synthesis of the first and second F₁ fields of the embodiment ofFIG. 10 is equivalent to the F₁ field of the line multiple speed system(see FIG. 8C), while the synthesis of the first and second F₂ fields ofthe embodiment shown in FIG. 10 becomes equivalent to the F₂ field ofthe line multiple speed system.

As described above, according to the embodiment of FIG. 10, since thecycles of the vertical synchronizing signal P_(VN*) supplied to thevertical deflecting circuit 12 are equal to one another, the respectivevertical periods become equal to one another and thus there occurs nosuch disadvantage that the jitter will be produced by the fluctuation ofeach vertical period. Further, since the interlace-ratio is keptconstant, it is possible to obtain the picture of good quality.According to this embodiment, since the reading of the first and secondF₂ fields is carried out with a delay of 0.5 H, the continuity of thehorizontal synchronization can be maintained similarly to the example ofFIG. 3 and thus no trouble occurs.

FIG. 12 shows another embodiment of the television receiver according tothe present invention, in which like parts corresponding to those ofFIGS. 3 and 10 are marked with the same references and will not bedescribed in detail.

In the embodiment of FIG. 12, instead of controlling the reading outtiming from the memories 16a and 16b, there is used a delay line.

In the embodiment of FIG. 12, the change over of the switching circuits16c and 16d and the write-in and/or read-out from the memories 16a and16b are carried out similarly to those of the example of FIG. 3 and fromthe switching circuit 16d , there is derived a field twice the normalspeed video signal Sv* such as shown in FIG. 4B.

Further, in the embodiment of FIG. 12, the video signal Sv* converted tothe analog signal by the D/A converter 7 is supplied to one fixedcontact 23a of a switching circuit 23 and also through a delay line 24having a delay amount of 0.5 H (corresponding to one line) to the otherfixed contact 23b thereof. This switching circuit 23 is changed inposition to the side of the contact 23a during the first and second F₁fields of the video signal Sv*, while it is changed in position to theside of the contact 23b during the first and second F₂ fields of thevideo signal Sv*. Accordingly, from this change-over switch 23, there isderived a video signal S_(VN*) (shown in FIG. llB) similar to that ofthe embodiment of FIG. 10 and this video signal is fed to the signalprocessing circuit 8.

Further, the video signal S_(VN) * derived from the switching circuit 23is supplied to the horizontal synchronizing separating circuit 14.

The other circuit elements are arranged similar to those of the examplesof FIGS. 3 and 10.

As a result, also in this embodiment of FIG. 12, the display similar tothat of the embodiment of FIG. 10 is made and similar action and effectcan be achieved.

In the embodiments of FIGS. 10 and 12, while the vertical deflectingcircuit 12 is supplied with the vertical synchronizing signal P_(VN) *from the control circuit 17, it is possible that instead of thesynchronizing signal P_(VN) * , the vertical synchronizing signal Pv,which is supplied from the synchronizing separating circuit 18, ismultiplied by two and then supplied to the vertical deflecting circuit.

FIG. 13 shows another embodiment of the television receiver according tothe present invention, in which like parts corresponding to those ofFIG. 6 are marked with the same references.

In the embodiment of FIG. 6, the display equivalent to the interlacedsystem of 312.5 lines/100 fields and 2:1 is carried out so that theflicker on the picture screen can be suppressed and the respectivevertical cycles become equal to each other, thus requiring no specialdeflection correcting circuit. However, if such a construction isemployed in which the arrangement of the scanning line as shown in FIG.8D is used or two scanning lines are continuously formed by the samesignal, there occurs a problem that a distortion of step-shape, i.e., aso-called "zig-zag" becomes conspicuous on the inclined portion. This"zig-zag" is described in greater detail in the Japanese patentapplication (patent application Ser. No. 23998/1983) which was filed bythe present applicant.

The embodiment of FIG. 13 is the example for reducing this "zig-zag".

In the figure, the video signal S_(VN) ' analog signal by the D/Aconverter 7 is supplied to an adder 26 which forms a predicting circuit25. This video signal S_(VN) ' is further supplied through a delay line27 having a delay amount of 0.5 H (corresponding to one line) to onefixed contact 28a of a switching circuit 28 and the adder 26. Then, inthis adder 26, the video signal S_(VN) ' and the signal, which resultsfrom delaying this video signal by 0.5 H, are added to each other andthen averaged. This added and averaged signal is supplied to the otherfixed contact 28b of the switching circuit 28. This switching circuit 28is changed in position to the side of contact 28a during the first F₁field and the second F₂ field of the video signal S_(VN) '. (shown inFIG. 7B), while it is changed in position to the side of the contact 28bduring the second F₁ field and the first F₂ field of the video signalS_(VN) '. That is, from the switching circuit 28, there are derived asignal, which results from delaying the video signal S_(VN) ' by 0.5 H,in the first F₁ field and the second F₂ field of the video signal S_(VN)' and a signal, which results from adding and averaging the video signalS_(VN) ' and the signal thereof delayed by 0.5 H, in the second F₁ fieldand the first F₂ field of the video signal S_(VN) ', respectively.

The signal derived from the switching circuit 28 is supplied to thesignal processing circuit 8.

Further, in FIG. 13, a delay line 29 having a delay amount of 0.5 H isconnected between the multiplier 11 and the vertical deflecting circuit12.

The other elements thereof are arranged similar to those of theembodiment shown in FIG. 6.

The scanning line arrangement and the field arrangement in theembodiment of FIG. 13 become as shown in FIG. 8F. As will be clear fromthis figure, in the embodiment of FIG. 13, the two scanning lines by thesame signal are not formed continuously but the interpolation signal isformed by adding and averaging the preceding and following scanninglines so that the above-described so-called "zig-zag" can be alleviated.

FIG. 14 shows another embodiment of the present invention which is acolor television receiver. In this case, after the luminance signal Yand the chrominance signal C are separated from each other, there isused the predicting circuit 25 as shown in the embodiment of FIG. 13.

In the figure, the video signal S_(VN) ' from the converting ing circuit6 is supplied to a luminance signal/chrominance signal separatingcircuit 30. The luminance signal Y from this separating circuit 30 issupplied through the predicting circuit 25 and a D/A converter 7Y to amatrix circuit 31. The chrominance signal C from the separating circuit30 is supplied to a color demodulating circuit 32 and this colordemodulating circuit 32 produces, for example, a red color differencesignal R-Y and a blue color difference signal B-Y which then arerespectively supplied through D/A converters 7R and 7B to the matrixcircuit 31. Then, from the matrix circuit 31, there are produced red,green and blue primary color signals R, G and B which are respectivelyfed to a picture receiving tube (not shown in FIG. 14).

The output from the D/A converter 7Y is supplied to the horizontalsynchronizing separating circuit 14.

The other portions are formed similarly to those of the embodiment ofFIG. 6.

In this case, although the predicting circuit 25 may be provided in thechrominance signal system, if it is omitted, the color televisionreceiver of this embodiment becomes inexpensive.

As the embodiment in which the predicting circuit 25 is provided, theembodiments of FIGS. 13 and 14 each of which corresponds to theembodiment of FIG. 6 are illustrated. However, it is possible tosimilarly consider the embodiments which correspond to the embodimentsof FIGS. 9, 10 and 12.

While in the above-described embodiments the video signal of theinterlaced system having 625 lines/50 fields and 2:1 was described, thepresent invention is not limited to the above interlaced system videosignal but can be similarly applied to the video signal of otherinterlaced system. Further, while in the above-embodiments, the fieldfrequency is selected to be twice, the present invention is not limitedto the above field frequency but can be similarly applied to a case inwhich the field frequency is converted to be three times, four times, .. .

EFFECT OF THE INVENTION

According to the present invention as mentioned above, since therespective vertical cycles are made equal to one another, the horizontaldeflecting current waveform on which, for example, the parabolic wavecurrent of the vertical cycle is superposed becomes equal during eachvertical period so that the jitters at the right and left ends of thepicture screen are not produced. Accordingly, no such special correctingcircuit for removing the jitter is required. Furthermore, according tothe present invention, since the interlace-ratio is kept constant, it ispossible to obtain a good picture.

We claim:
 1. A television receiver comprising:scan converter meansincluding field-memory means supplied with an input video signal of aninterlaced television signal having a first field rate and apredetermined interlace-ratio, said field memory means including aplurality of one-field memories, memory control means supplying writingand reading signals to said field-memory means where a frequency of saidreading signal is greater than a frequency of said writing signal forreading out a plurality of fields at a second field rate greater thansaid first field rate, and an output terminal for deriving an outputvideo signal; video display means supplied with said output videosignal; and deflection means including vertical deflection means forvertically deflecting said video display means with a verticalsynchronizing signal having a constant period, characterized by timingcontrol means for delaying the reading out of at least two selected onesof said plurality of fields and controlling the timing of said outputvideo signal at a vertical rate such that a picture reproduced on saidvideo display means has an interlace-ratio equal to said predeterminedinterlace-ratio,
 2. A television receiver according to claim 1, whereinsaid timing control means is provided in said memory control means andcontrols the timing of said reading signal.
 3. A television receiveraccording to claim 1, wherein said timing control means is formed as adelay compensation circuit operated at a vertical rate and said delaycompensation circuit is inserted between said scan converter means andsaid video display means.
 4. A television receiver according to claim 3,wherein said interlace ratio is 2:1, said second field rate is two timessaid first field rate, and said delay compensation circuit provides atime delay of one-quarter of a horizontal scanning period.
 5. Atelevision receiver according to claim 4, wherein said field memorymeans comprises first and second one-field memories and said memorycontrol means causes readout of said first one-field memory twice insuccession and subsequent read out of said second one-field memory twicein succession.
 6. A television receiver according to claim 5, whereinsaid vertical rate is selected to insert said delay compensation meansto delay the second read out of said first one-field memory and to delaythe first read out of said second one-field memory.
 7. A televisionreceiver according to claim 3, wherein said interlace ratio is 2:1, saidsecond field rate is two times said first field rate, and said delaycompensation circuit provides a time delay of one-half of a horizontalscanning period.
 8. A television receiver according to claim 1, whereinsaid interlace ratio is 2:1 and said second field rate is two times saidfirst field rate.
 9. A television receiver according to claim 8, whereinsaid field memory means comprises first and second one-field memoriesand said memory control means causes read out of said first one-fieldmemory twice in succession and subsequent read out of said secondone-field memory twice in succession.
 10. A television receiveraccording to claim 9, wherein said timing control means delays thesecond read out of said first one-field memory and delays the first readout of said second one-field memory by a fraction of a horizontalscanning period.
 11. A television receiver according to claim 10,wherein said fraction consists of one-quarter of a horizontal scanningperiod.
 12. A television receiver according to claim 10, wherein saidfraction consists of one-half of a horizontal scanning period.